The processing and transfer of mass data at high speeds have become necessary in recent years. This has resulted in the necessity for high-speed interfaces. A high-speed interface that enables the transfer of data in a Gbps band does not transfer data in synchronization with a clock (synchronous data transfer) as in a conventional manner. Rather, a high-speed interface is required to perform non-synchronous transfer. Accordingly, a reception node must have a clock data recovery (CDR) circuit that generates a clock (synchronization clock) synchronized with the received data.
Japanese Laid-Open Patent Publication No. 2005-150890 (paragraph 0026 and FIGS. 1 and 3) describes such a CDR circuit. The CDR circuit, which has an analog circuit configuration, increases the response sensitivity when the phase difference between the clock and data is large and decreases the response sensitivity when the phase difference between the clock and data is small. However, a CDR circuit having an analog configuration is not appropriate for a high-speed interface.
Japanese Laid-Open Patent Publication No. 2005-257376 (FIG. 1) describes a CDR circuit including a phase comparator, a serial/parallel converter, and a digital filter. The CDR circuit uses a digital filter in lieu of a low-pass filter (LPF) that is used in the CDR circuit of Japanese Laid-Open Patent Publication No. 2005-150890.
FIG. 1 is a block diagram showing the circuit configuration of a conventional serial interface, such as IEEE1394.b, together with the flow of data. As shown in FIG. 1, a transmission node 80 includes a parallel/serial converter 81 and a transmitter 82. The parallel/serial converter 81 converts parallel transmission data to serial transmission data and provides the converted data to the transmitter 82. The transmitter 82 transmits the transmission data as differential serial data from the parallel/serial converter 81 to a reception node 90.
The reception node 90 includes a receiver 91, a CDR circuit 92, and a serial/parallel converter 93. The receiver 91 provides the CDR circuit 92 with the differential serial data transferred from the transmission node 80 (transmitter 82) as single end serial data. The CDR circuit 92 generates a clock synchronized with the single end serial data, or received data. Further, the CDR circuit 92 synchronizes the single end serial data with the synchronization clock to generate synchronized serial data. The serial/parallel converter 93 converts the synchronized serial data generated by the CDR circuit 92 into parallel data, which is provided to various processing circuits in the following stage.
When an internal circuit of the reception node 90 is affected by noise or the like and fails to function normally, the synchronization clock may not be properly generated even though data reception is started. In such a case, the communication between connection nodes (i.e., the transmission node 80 and the reception node 90) may be interrupted. Further, even when the synchronization clock is properly generated and data transfer is started, the clock synchronization may be lost during the data transfer. This may interrupt communication between connection nodes.
FIG. 2 is a flowchart showing synchronization procedures for the reception node 90 in the prior art. A serial interface, such as IEEE1394.b, transmits and receives synchronization data to perform synchronization between connection nodes. The reception node 90 receives the synchronization data (step S91).
The synchronization data includes a synchronization detection character code line (hereafter simply referred to as character code line). The reception node 90 detects the character code line. Then, when receiving the synchronization data in a normal manner over a given time, the reception node 90 determines that synchronization has been established with a peer node, namely, the transmission node 80. The CDR circuit 92 generates a synchronization clock when determining synchronization establishment.
More specifically, the reception node 90 starts a process for detecting a character code line when, for example, the transmission node 80 starts to transmit data and then checks whether or not synchronization data has been normally received over a given period (step S92). During a given synchronization detection time N, if a character code line cannot be detected and synchronization data cannot be received over the given period, the reception node 90 performs a connection failure process (step S93). During the synchronization detection time N, if a character code line is detected and synchronization data is received, the reception node 90 acknowledges establishment of synchronization and starts normal data reception (step S94). The synchronization detection time N is determined in accordance with the data transfer standard (e.g., several tens of milliseconds for IEEE1394.b).
After normal data reception starts, the reception node 90 constantly determines whether the received data is a string of data that does not comply with the data transfer standard (step S95). When determining that a non-compliant data string has been received, the reception node 90 determines that synchronization has been lost and performs a connection interruption process (step S96). A non-compliant data string refers to a data string that is not specified by the data transfer standard. For example, in IEEE1394.b, lost synchronization is determined when a data pattern is not generated through 8B/10B encoding.
A defect that occurs in the CDR circuit 92 may hinder the establishment of synchronization between connection nodes. In such a case, even though the CDR circuit 92 generates the synchronization clock within a shorter period than the synchronization detection time N, communication failure would be determined only after the detection time N elapses. This would be a waste of time.
Further, even if synchronization is established between connection nodes, noise may seriously affect the CDR circuit 92 such that synchronization is lost and connection nodes are disconnected.